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HFA3663
Data Sheet January 1999 File Number
4241.3
2.3GHz UpConverter with Gain Control
The HFA3663 UpConverter with Gain Control is a monolithic bipolar device for up conversion applications in the 2.0GHz to 2.3GHz range. Manufactured in the Intersil UHF1X process, the device consists of a double balanced mixer followed by a variable gain power preamp. An energy saving, TTL Compatible, power enable input provides on/off bias current control to the mixer and amplifier. The device requires low drive levels from the local oscillator and is housed in a small outline 20 lead SSOP package ideally suited for PCMCIA card applications.
TM
Features
* RF Frequency Range . . . . . . . . . . . . . . 2.0GHz to 2.3GHz * IF Operation . . . . . . . . . . . . . . . . . . . . . 10MHz to 400MHz * Gain Control Range . . . . . . . . . . . . . . . . . . . . . . . . . .20dB * Single Supply Operation. . . . . . . . . . . . . . . . . 2.7V to 5.5V * High Output 1dB Compression. . . . . . . . . . . . . . . . . 6dBm * High Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .18dB * Power Enable/Disable Control
Applications
* Wireless Local Loop Systems * PCMCIA Wireless Transceiver
Ordering Information
PART NUMBER HFA3663IA HFA3663IA96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld SSOP Tape and Reel PKG. NO. M20.15
* Wireless Local Area Network Modems * CDMA/TDMA Packet Protocol Radios * Full Duplex Transceivers * Portable Battery Powered Equipment
Pinout
HFA3663 TOP VIEW
PRE_VCC3 GND PRE_OUT GND PRE_VCC2 GND BIAS_VCC GND PRE_IN 1 2 3 4 5 6 7 8 9 20 TX_PE 19 LO_BY 18 LO_IN 17 GND 16 IF_IN 15 IF_BY 14 GND 13 TXM_RF 12 MIX_VCC 11 AGC_CTRL
Block Diagram
BIAS_VCC
BIAS PRE_OUT PRE_VCC3
TX_PE LO_BY LO_IN IF_IN IF_BY
PRE_VCC2
PRE_VCC1 PRE_IN TXM_RF
PRE_VCC1 10
AGC CONTROL
AGC_CTRL
POWER CONTROL TRUTH TABLE STATE Power Down - Energy Saving Mode Transmit Mode TX_PE Low High
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3663 Typical Application Diagram
PRISMTM FULL DUPLEX CHIP SET
HFA3424/21 (FILE #4131) D U P L E X E R LNA BPF HFA3661 (FILE #4240) LNA RF/IF CONVERTER RF LO1 HFA3524 (FILE #4062) SYNTHESIZER IF LO1 BASEBAND HFA3524 (FILE #4062) HFA3925 (FILE #4132) PA BPF SYNTHESIZER RF LO2 AGC IF/RF CONVERTER HFA3663 (FILE #4241) HFA3664 (FILE #4242) AGC QMODEM LPF OPTIONAL WHEN IN ANALOG MODE PRISMTM FULL DUPLEX RADIO CHIP SET, FILE #4238 IF LO2 HFA3763 (FILE #4237) LPF D/A HFA3761 (FILE #4236) FILTER IF AGC QMODEM LPF LPF A/D
Pin Description
NAME LO_IN LO_BY PRE_IN PRE_OUT PRE_VCC1 PRE_VCC2 PRE_VCC3 BIAS_VCC MIX_VCC RX_PE TXM_RF IF_IN IF_BY GND Local Oscillator Input. Local Oscillator Input Bypass (AC coupled to GND). Power Pre-Amplifier Input. Power Pre-Amplifier Output. Power Pre-Amplifier 1st Stage Positive Power Supply. Use high quality RF decoupling capacitors. Power Pre-Amplifier 2nd Stage Positive Power Supply. Use high quality RF decoupling capacitors. Power Pre-Amplifier 3rd Stage Positive Power Supply. Use high quality RF decoupling capacitors. LO Buffer, Bias, Mixer and AGC Control Positive Power Supply. Requires an isolation coil to VCC. Transmit Mixer Output Stage Positive Power Supply. Use high quality RF decoupling capacitors. Power Enable Control Input. Refer to the Power Control Truth Table. Transmit Mixer RF Output. Transmit Mixer Positive IF Input. Requires external bias resistor to VCC. Transmit Mixer Negative IF Input (AC coupled to GND). Circuit Ground Pins (Qty 6). Internally connected with the exception of pin 17. DESCRIPTION
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HFA3663
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . . -0.3 to VCC 0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 20 Lead SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Package Power Dissipation at 70oC 20 Lead SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7W Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Temperature Range. . . . . . . . . . . . . . . -40oC TA 85oC Maximum Storage Temperature Range . . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VCC = 5.5V, LO = 2050MHz, IF = 100MHz, RF = 2150MHz, ZO = 50, Unless Otherwise Specified (NOTE 2) TEST LEVEL TEMP (oC)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CASCADED CHARACTERISTICS (-3dB Loss RF Image Filter with 35dB LO Suppression, LO_IN = 2050MHz/-6dBm, IF_IN = 100MHz/-30dBm, AGC_CTRL = 0.7V (Max Gain)) Cascaded Output 1dB Compression Cascaded Output Third Order Intercept Cascaded Power Gain Cascaded Power Gain Flatness (2.0GHz to 2.3GHz) Cascaded LO Leakage CTX_P1D CTX_IP3 CTX_PG CTX_PGF CTX_LEAK B C B C B 25 25 25 25 25 6 18 -2.5 7.5 14 22 0 -20 +2.5 dBm dBm dB dB dBm
LO INPUT CHARACTERISTICS (LO_IN = 2050MHz/-6dBm, all unused inputs and outputs are terminated into 50) LO Input Frequency Range LO Input Drive Level LO Input VSWR LO Input Return Loss LO_f LO_dr LO_SWR LO_IRL B A A A 25 25 25, 85 25, 85 1.6 9.4 -6 1.62:1 12.5 2.29 2.0:1 GHz dBm dB
TRANSMIT MIXER CHARACTERISTICS (LO_IN = 2050MHz/-6dBm, TXM_IF = 100MHz/-30dBm) IF Input Frequency Range IF Input VSWR IF Input Return Loss Power Conversion Gain (Note 3) Transmit Mixer LO Leakage RF Output Frequency Range RF Output VSWR RF Output Return Loss RF Output 1dB Compression (Note 3) RF Output Third Order Intercept Transmit Mixer Noise Figure VCC = 5.5V VCC = 5.5V TXM_IFf TXM_SWR TXM_IRL TXM_PGH TXM_LEAK TXM_RFf TXM_OSWR TXM_ORL TXM_P1DH TXM_IP3 TXM_NF B A A A A B A A A C B 25 25, 85 25, 85 25, 85 25, 85 25 25, 85 25, 85 25 25 25 10 9.4 3.0 2.0 9.4 -7.8 1.22:1 23 5.6 -20 1.68:1 17.4 -6.5 2.7 18 400 2.0:1 TBD -10 2.3 2.0:1 MHz dB dB dBm GHz dB dBm dBm dB
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HFA3663
Electrical Specifications
VCC = 5.5V, LO = 2050MHz, IF = 100MHz, RF = 2150MHz, ZO = 50, Unless Otherwise Specified (Continued) (NOTE 2) TEST LEVEL TEMP (oC)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TRANSMIT POWER PREAMP CHARACTERISTICS (PRE_IN = 2150MHz/-30dBm, AGC_CTRL = 0.7V (Max Gain)) Frequency Range Power Gain (AGC_CTRL = 0.7V) VCC = 5.5V PRE_f PRE_PGH PRE_NF PRE_AGC AGC_V AGC_LIN AGC_T1 AGC_T2 PRE_P1DH PRE_IP3 PRE_ISWR PRE_IRL PRE_OSWR PRE_ORL B A B A A B B B A C A A A A 25 25, 85 25 25 25 25 25 25 25 25 25, 85 25, 85 25, 85 25, 85 2.0 18 20 0.7 8 6.02 1.0 9.4 24 8 30 5:1 8.0 0.1 10 17 2.7:1 9.0 1.17:1 15.4 2.3 1.7 3.0:1 2.0:1 GHz dB dB dB V S S dBm dBm dB dB
Pre-Amp Noise Figure (Max Gain) Pre-Amp AGC Range (Max - Min Gain) AGC Control Voltage Range AGC Control Linearity AGC Settling Time (Min to Max Gain) AGC Settling Time (Max to Min Gain) Pre-Amp RF Output 1dB Compression RF Output Third Order Intercept Input VSWR Input Return Loss Output VSWR Output Return Loss POWER SUPPLY AND LOGIC CHARACTERISTICS Voltage Supply Range Supply Current (VCC = 5.5V) VCC = 5.5V
VCC ICC HI ICC HIT
A A C A A A A A A A B B
25 25, 85 Full 25 25 25 25 25 25 25 25 25
4.5 9.0 0.004 -0.2 2.0 -400 -
100 2.8 -5.0 -5.0 10 -10 5 0.1
5.5 110 110 4 0.8 VCC 5.0 5.0 400 10 10
V mA mA mA V V A A A A s s
Power Down Supply Current (VCC = 5.5V) Logic Input Low Level Logic Input High Level Logic Low Input Bias Current (VPE = 0V, VCC = 5.5V) Logic High Input Bias Current (VPE = 5.5V, VCC = 5.5V) Vagc High Input Bias Current (Vagc = 2.1V, VCC = 5.5V) Vagc Low Input Bias Current (Vagc = 0.7V, VCC = 5.5V) Power Enable Time (50% VPE to 90% ICC) Power Disable Time (50% VPE to 10% ICC) NOTES:
ICC_PD VIL VIH IB_LO IB_HI Ivagc_HI Ivagc_LO PEt PDt
2. Test Level: A = 100% production tested, B = Typical or Limit based on characterization data, C = Design information, goal or condition. 3. Bias Resistor at pin 16 changes according to the relationship mentioned in Note 4 of the Typical Applications Circuit.
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HFA3663 Typical Application Circuit
VCC = 5.0V TRANSMIT ENABLE
C1 2.2F
C2 3300pF
7pF PRE_VCC3 1 C3 330pF RF OUTPUT 50 C4 7pF 7pF C5 22pF GND PRE_OUT 3 GND PRE_VCC2 GND BIAS_VCC 4.7nH GND C7 7pF C8 330pF PRE_IN 9 PRE_VCC1 7pF 10
AGC CONTROL
TX_PE 20 LO_BY C9 2 19 LO_IN 7pF 18 17 16 IF_BY 6 7 8 15 14 13 12 11 330pF AGC CONTROL MIX_VCC AGC_CTRL GND 3300pF C12 GND IF_IN 5 NOTE 4 1.69K
330pF
7pF C10 C11 3300pF LO INPUT 50
4
IF INPUT 50
TXM_RF
C13 7pF C14 7pF C15 3300pF
NOTE 5
50 BPF LO REJECT FILTER
NOTE 5
NOTES: 4. Required external resistor for Mixer biasing. Value optimized for 2.7mA bias current with R = (VCC - 0.93)/2.7mA. Most Mixer cell characteristics like Gain, NF etc., can be affected when biasing is outside the optimum value. 5. The combination of these attenuator pads and the Band Pass Filter insertion loss shall bring the overall Cascaded Gain at the desired frequency of operation from 21dB to 22dB for best performance. The selection of these values is optional. The total gain, LO feedthru, Mixer and Preamplifier interaction (stability) and output compression point performances can be manipulated according to the user needs.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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